This invention relates to the field of integrated circuit devices and, more particularly, a method of manufacturing highly packed memory cell capacitance devices for highly integrated dynamic RAMs and the resulting structure.
Present day dynamic random access memory (RAM) devices have many thousands of individual memory cells, each comprising a transistor and a capacitor. The capacitor can hold one bit of information by being in a changed state or an uncharged state; the transistor acts as a switch to electrically connect the capacitor to the rest of the RAM device so that information may be read from the capacitor or written into the capacitor.
Ideally, a memory cell capacitor should have a large capacitance per unit area. This permits the capacitor to be physically small so as to densely packed to permit a very high degree of integration in a semiconductor substrate without requiring an increased sensitivity of the sense amplifier which would read the amount of charge stored on the capacitor. Efforts to achieve a high capacitance per unit area memory cell has resulted in the so-called "Hi-C" RAM memory cell disclosed by C. G. Sodini and T. I. Kamins in their paper, "Enchanced Capacitor for One-Transistor Memory Cell," IEEE Trans. Electron Devices, Vol. ED-23, pp. 1187-1189, October 1976 and further expanded by A. F. Tasch, et al., "The Hi-C Ram Cell Concept," IEEE Trans. Electron Devices, Vol. ED-25, No. 1, pp. 33-41, January 1978.
This concept involves the implantation of an impurity layer of one polarity above a second impurity layer of another polarity in a semiconductor substrate. A capacitor oxide layer is formed on the substrate and a conductive layer is laid on top of the oxide layer to form the capacitance device. This structure has an enhanced capacitance because there are two components of capacitance. The first is the oxide capacitance, the capacitance between the conducting layer over the gate oxide and the substrate below; the second is the depletion layer capacitance, which is formed by the juxtaposition of the two implanted dopant layers of opposing polarities. This structure contrasts with the standard structure of a dynamic RAM cell capacitor which has only the oxide capacitance. The new structure has a much greater capacitance per unit area.
The present invention is a method of manufacturing Hi-C memory cell capacitance device by which such capacitors may be packed together to the greatest extent possible for a particular processing technology and the resulting device structure therefrom. With the present invention, each of the capacitor devices is cearly defined with respect to another device so that each capacitor remains electrically isolated from others to retain its electrical integrity. Savings in semiconductor substrate space is achieved and the integration of the entire RAM device is enhanced.